The present disclosure relates generally to information handling systems, and more particularly to detection of a reversal of lanes of an interface in an information handling system.
As the value and use of information continues to increase, individuals and businesses seek additional ways to process and store information. One option available to users is information handling systems. An information handling system generally processes, compiles, stores, and/or communicates information or data for business, personal, or other purposes thereby allowing users to take advantage of the value of the information. Because technology and information handling needs and requirements vary between different users or applications, information handling systems may also vary regarding what information is handled, how the information is handled, how much information is processed, stored, or communicated, and how quickly and efficiently the information may be processed, stored, or communicated. The variations in information handling systems allow for information handling systems to be general or configured for a specific user or specific use such as financial transaction processing, airline reservations, enterprise data storage, or global communications. In addition, information handling systems may include a variety of hardware and software components that may be configured to process, store, and communicate information and may include one or more computer systems, data storage systems, and networking systems.
Many information handling systems include peripheral devices that may be connected to the information handling system via a motherboard. For example, network cards, video cards, port expansion cards, storage devices, and/or a variety of other peripheral devices may be coupled to the motherboard using high-speed serial links in order to enhance the capabilities and performance of the information handling system. Peripheral Component Interconnect Express (PCIe) is a standard for such high-speed serial links between the motherboard and the peripheral device, and provides for communication between PCIe devices via a logical connection (a “link”), which is a point-to-point communication channel between two PCIe ports that allows for the sending and receiving of PCIe requests and interrupts. At the physical level, a link may include one or more lanes, and a lane may include two differential signaling pairs, with one pair utilized for receiving data and the other pair utilized for transmitting data. Thus, each lane may include four wires or signal traces. Conceptually, each lane may be used as a full-duplex byte stream, transporting data packets in an eight-bit “byte” format simultaneously in both directions between endpoints connected to a link. Physical PCIe links typically include from one to 32 lanes and, more precisely, 1 lane, 2 lanes, 4 lanes, 8 lanes, 12 lanes, 16 lanes, or 32 lanes, with PCIe links typically operating at transfer rates of 2.5 GT/s, 5.0 GT/s, 8.0 GT/s, 16.0 GT/s, or 32 GT/s.
An auto-bifurcation feature may be provided by a Basic Input/Output System (BIOS) that logically partitions lanes of a PCIe slot on the motherboard into one or more root ports during the boot of the motherboard. This allows a single PCIe slot to be coupled to one or more peripheral devices by automatically determining a lane width of those devices, and creating a root port having the same lane width. For example, a 16 lane PCIe slot may be bifurcated into 4 root ports that are each coupled to 4 lanes, 2 root ports each that are each coupled to 8 lanes, 1 root port that is coupled to 16 lanes, 3 root ports that include 1 root port that is coupled to 8 lanes and 2 root ports that are each coupled to 4 lanes, and so on. As such, in the example of 4 root ports that are each coupled to 4 lanes, 4 peripheral devices each having 4 lanes may be coupled to the PCIe slot. Bifurcating PCIe slots provides increased flexibility with regard to the types of peripheral devices that can be coupled to the motherboard without requiring specific PCIe slots for those devices. The auto-bifurcation feature also allows the BIOS to detect these configurations automatically so that a system administrator does not have to manually configure each PCIe slot.
However, conventional bifurcation techniques run into issues when lane reversal is implemented between the peripheral device and the PCIe slot. Lane reversal is a feature that provides flexibility in hardware platform design, layout, and routings, and is used by platform designers to simplify or reduce the number of layers on a printed circuit board in order to, for example, improve high speed signaling, achieve lane-to-lane length matching design rules, and/or for other benefits that would be apparent to one of skill in the art. However, bifurcation algorithms have to account for lane reversal in order to determine the correct bifurcation setting(s). For example, the lane reversal information may be gathered by the BIOS by reading manually coded information regarding which PCIe slots or PCIe ports are routed as a lane reversed crosslink. That lane reversal information is manually coded because there is no reporting mechanism that the BIOS can use to discover the lane reversal. Thus, conventional systems assume a preferred routing such as, for example, reversed or non-reversed routings, and the peripheral device may be tested to determine whether it is responsive or not based on the preferred routing. If the peripheral device is not responsive, an administrator may reset the system to change the lane reversal setting for the bifurcation setting. However, this solution increases boot time.
In another conventional system, the BIOS has knowledge of which slots or PCIe ports have a lane reversed routing, and that information is fed into the bifurcation algorithm, which allows the BIOS to select the correct bifurcation setting on the first pass and without the need for extra resets and their associated increased boot times. However, this solution limits the number of supported configurations on the system.
Accordingly, it would be desirable to provide an improved bifurcation system with lane reversal detection.